1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and a structure of a semiconductor device, and more particularly to a method of manufacturing a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a structure thereof.
2. Description of the Background Art
With miniaturization of semiconductor devices, a technique of forming a metal silicide for use in gate, source and drain has been in actual use as one of attempts to increase drain currents of a MOSFET for high-speed operation of circuits. A characteristic feature of the metal silicide lies in its lower resistance value than that of a doped polysilicon. In order to form the metal silicide, a refractory metal film is deposited on a silicon and then a heat treatment such as RTA (Rapid Thermal Annealing) is performed to react the silicon with the refractory metal film. Forming the metal silicide for use in the gate, source and drain lowers the resistance values of the respective regions, thereby increasing the drain currents.
Among kinds of metal suicides well known are a titanium silicide (TiSi2), a tungsten silicide (WSi2), a nickel silicide (NiSi), a platinum silicide (PtSi), a cobalt silicide (CoSi2) and the like. Among them, it is known that even when used in a fine gate electrode whose gate length is 0.1 xcexcm or less, the cobalt silicide can lower the resistance of the gate electrode. On the other hand, it is known that when used in a gate electrode whose gate length is 0.15 xcexcm or less, the tungsten silicide increases the resistance of the gate electrode by the linewidth effect. The cobalt silicide, nickel silicide or platinum silicide does not have the linewidth effect.
Now, reaction of cobalt (Co) with silicon (Si) will be discussed. At 400xc2x0 C., Co begins to react with Si, thereby forming a Co2Si, and the sheet resistance gradually becomes higher. At 450 to 500xc2x0 C., a CoSi is formed and the sheet resistance becomes maximum. Over 600xc2x0 C., a CoSi2 is formed and the sheet resistance becomes lower.
In the process of forming the cobalt silicide, first, a first RTA is performed at 450 to 600xc2x0 C. Next, an unreacted Co is removed and then a second RTA is performed at 650 to 800xc2x0 C. to lower the sheet resistance. Further, when the temperature for the second RTA rises up to 900xc2x0 C., as the Co in the metal silicide is diffused into a silicon substrate, reaching the vicinity of a pn junction of source/drain regions, the amount of leakage currents increases.
FIG. 28 is a cross section showing a structure of a general-type MOSFET in which the cobalt silicide is formed. In an upper surface of a silicon substrate 101, an STI (Shallow Trench Isolation) 102 is selectively formed. On the upper surface of the silicon substrate 101, a gate electrode 104 is selectively formed with a gate insulating film 103 interposed therebetween. On the gate electrode 104, a cobalt silicide 106 is formed. Further, in the upper surface of the silicon substrate 101 formed are source/drain regions 111 which are paired with a channel region which is formed below the gate electrode 104 interposed therebetween, being in contact with side surfaces of the STI 102. On the source/drain regions 111, cobalt silicide layers 112 are formed. On side surfaces of the gate electrode 104, sidewalls 109 are formed with first and second offset films 107 and 108 interposed therebetween.
The reaction of silicidation proceeds through diffusion of refractory metal towards the silicon. Therefore, as shown in FIG. 28, the cobalt intrudes into an interface between the second offset film 108 and the silicon substrate 101, to form an intruding portion 114 of the cobalt silicide layer 112. Further, the cobalt intrudes into an interface between the STI 102 and the silicon substrate 101, to form an intruding portion 115 of the cobalt silicide layer 112.
With miniaturization of the semiconductor devices, when the width of the sidewall 109 becomes 10 nm or less, the intruding portion 114 of the cobalt silicide layer 112 reaches the gate insulating film 103 and the amount of leakage currents at the gate thereby increases. Further, when the depth of the pn junction formed at an interface between the source/drain region 111 and the silicon substrate 101 becomes shallower than the depth of 0.05 xcexcm from the upper surface of the silicon substrate 101, the intruding portion 115 of the cobalt silicide layer 112 reaches a depletion layer of the pnjunction and the amount of leakage currents at the source and drain thereby increases.
Furthermore, in a reaction process of silicidation, the metal silicide sometimes abnormally grows like a spike due to a stress in the phase transition of crystal, and the like. In FIG. 28 shown is an abnormally-grown spike 113 of the cobalt silicide. The cobalt silicide abnormally grows at the temperature of 400 to 450xc2x0 C., to form the spike 113. With miniaturization of the semiconductor devices, when the depth of the pn junction formed at the interface between the source/drain region 111 and the silicon substrate 101 becomes shallower than the depth of 0.1 xcexcm from the upper surface of the silicon substrate 101, the spike 113 reaches the depletion layer of the pn junction and the amount of leakage currents at the source and drain thereby increases.
As one of methods for suppressing generation of the spike which is caused by abnormal growth of the cobalt silicide well known is a preamorphization method. In this method, nitrogen or germanium is ion-implanted to amorphize the silicon substrate in advance before a cobalt film is deposited, and then the cobalt silicide is formed. Preamorphization of the silicon substrate relieves a stress caused at an interface between the silicide and the silicon on reaction, to suppress generation of the spike.
FIGS. 29 to 35 are cross sections showing a method of manufacturing an N-type MOSFET by the preamorphization method in the background art step by step. Referring to FIG. 29, first, the STI 102 is selectively formed in the upper surface of the silicon substrate 101. Subsequently, ion implantation is performed to form a well, a channel stopper layer and a channel dope layer (all not shown). Next, a silicon oxide film 120 is formed on the upper surface of the silicon substrate 101. Subsequently, an amorphous silicon film 121 is entirely deposited by the CVD (Chemical Vapor Deposition) method. Then, phosphorus ions 122 are implanted into the amorphous silicon film 121 by ion implantation.
Referring to FIG. 30, in the next step, the amorphous silicon film 121 and the silicon oxide film 120 are patterned by photolithography and anisotropic dry etching, to form the gate electrode 104 and the gate insulating film 103. Subsequently, a silicon-oxide-based insulating film such as a TEOS (Tetra Ethyl Ortho Silicate) film 123 is entirely deposited by the CVD method. With the temperature at this deposition, the amorphous silicon of the gate electrode 104 begins to become polysilicon (i.e., polycrystallize).
Referring to FIG. 31, in the next step, the TEOS film 123 is anisotropically etched, to form the first offset films 107 on the side surfaces of a gate structure consisting of the gate insulating film 103 and the gate electrode 104. Subsequently, arsenic ions 124 are implanted, to form extension regions 110 in the upper surface of the silicon substrate 101. Further, boron ions 125 are implanted, to form a pocket implantation region (not shown) in the silicon substrate 101. Forming the first offset film 107 is intended to protect the gate insulating film 103 in the ion implantation, to reduce variation in threshold voltage by increasing the effective channel length Leff and reduce the capacitance (gate overlap capacitance) formed between the gate electrode 104 and the extension region 110. Further, forming the pocket implantation region relieves roll-off of the threshold voltage and also suppresses occurrence of surface punch through. The arsenic ions 124 and the boron ions 125 are also implanted into the gate electrode 104.
Referring to FIG. 32, in the next step, a TEOS film 126 and a silicon nitride film 127 are entirely deposited in this order by the CVD method. With the temperature of this deposition, change of the gate electrode 104 into polysilicon further proceeds.
Referring to FIG. 33, in the next step, the silicon nitride film 127 and the TEOS film 126 are anisotropically etched, to form the sidewalls 109 and the second offset films 108. Subsequently, arsenic ions 128 are implanted, to form the source/drain regions 111. The arsenic ions 128 are also implanted into the gate electrode 104. Subsequently, in order to electrically activate the arsenic ions 124 and 128 and the boron ions 125, an RTA is performed at 1100xc2x0 C. With this heat treatment, the silicon substrate 101 is recovered from defects caused by the ion implantation. Further, with this heat treatment, a columnar grain having a grain boundary 105 which extends along a direction of film thickness of the gate electrode 104 is formed in the gate electrode 104.
Referring to FIG. 34, in the next step, in order to amorphize upper surfaces of the source/drain regions 111, in other words, for the above-discussed preamorphization, germanium ions (not shown) are implanted. Subsequently, by sputtering under an argon atmosphere, for example, a native oxide film (not shown) formed on the surfaces of the source/drain regions 111 is removed. Removing the native oxide film is intended to avoid an increase in resistance value of the metal silicide due to the presence of the native oxide film. Next, a cobalt film 129 and a titanium nitride film 130 are entirely deposited in this order. Forming the titanium nitride film 130 is intended to prevent an increase in sheet resistance through natural oxidation of the cobalt film 129, mixing of oxygen into the cobalt film 129 during conveyance of wafers and processing in the device, and the like.
Referring to FIG. 35, in the next step, the first RTA is performed at 400xc2x0 C. Subsequently, the titanium nitride film 130 and the unreacted cobalt film 129 are removed and then the second RTA is performed at 700xc2x0 C. An upper surface of the gate electrode 104 is thereby silicified to form the cobalt silicide layer 106 and the upper surfaces of the source/drain regions 111 are silicified to form the cobalt silicide layers 112.
The above-discussed method of manufacturing a MOSFET in the background art, however, has the following problems.
The First Problem
As shown in FIG. 33, in the gate electrode 104 formed is the columnar grain having the grain boundary 105 which extends along the direction of film thickness of the gate electrode 104. Since the diffusion coefficient of a dopant diffused along the grain boundary is higher than that of a dopant diffused in the grain, the dopant introduced into the gate electrode 104 is diffused mainly along the grain boundary 105 to reach an interface between the gate electrode 104 and the gate insulating film 103. To suppress gate depletion, it is desired to activate more dopant in the vicinity of this interface. When the amount of dopant reaching the vicinity of this interface becomes too large, however, part of the dopant penetrates the gate insulating film 103 to reach the inside of the silicon substrate 101 and as a result, the threshold voltage of the MOSFET goes out of the designed value. This phenomenon is referred to as xe2x80x9cpenetration of dopantxe2x80x9d.
To suppress variation in threshold voltage which is caused by the penetration of dopant, it is necessary to reduce the amount of dopant reaching the interface between the gate electrode 104 and the gate insulating film 103 by some method. Anyway, it is necessary to ion-implant the dopant into the gate electrode 104 densely to such a degree that the polysilicon can degenerate. Accordingly, simple reduction in dose to be ion-implanted into the gate electrode 104 causes some problems, such as an increase in resistance value of the gate electrode 104 and deterioration in current driving capability which is caused by gate depletion. Therefore, simple reduction in dose for ion implantation can not be adopted.
Thus, the background-art method of manufacturing a MOSFET has the problem of not appropriately suppressing variation in threshold voltage which is caused by the penetration of dopant.
The Second Problem
As can be seen from comparison between FIGS. 28 and 35, in the background-art method of manufacturing a MOSFET using preamorphization, it is possible to avoid or suppress generation of any spike 113 due to abnormal growth of silicide. It is not possible, however, to avoid generation of the intruding portions 114 and 115 of the cobalt silicide layer 112 even by the preamorphization method.
Thus, in the background-art method of manufacturing a MOSFET, the intruding portions 114 and 115 of the cobalt silicide layer 112 are still formed. Therefore, this method has a problem of increasing leakage currents at the gate, source and drain as the size of a semiconductor device becomes smaller.
Further, in the step of FIG. 30, the amorphous silicon film 121 is anisotropically etched to form the gate electrode 104, and the gas used in the step of anisotropic etching is free radical, such as CFx. Part of the free radical is accelerated by an electric field between a plasma sheath and a wafer in an etching device, to mix into the silicon substrate 101. The free radical which mixes into the silicon substrate 101 is dissociated into C atoms and F atoms through nuclear scattering caused by collision with silicon atoms. The F atoms become F2 molecule by the heat treatment or become HF molecule through chemical bond with hydrogen atoms in the silicon substrate 101, volatilizing out of the silicon substrate 101. In contrast, the C atoms remain inside the silicon substrate 101, disadvantageously, becoming a source of leakage current.
Furthermore, when the metal silicide is formed in a narrow region of about 0.15 xcexcm or less, the temperature required for phase transition from CoSi of high resistance to CoSi2 of lower resistance rises. Therefore, the metal silicide is flocculated when heated to high temperature, about over 800xc2x0 C., and the metal silicide is disadvantageously broken.
The Third Problem
To suppress the short-channel effect, there is a tendency of forming the extension regions 110 shallower in the upper surface of the silicon substrate 101. When the extension regions 110 are formed shallower, however, the sheet resistance becomes higher and accordingly the current driving capability of the MOSFET is disadvantageously deteriorated.
The present invention is directed to a method of manufacturing a semiconductor device. According to a first aspect of the present invention, the method of manufacturing a semiconductor device comprises the steps of: (a) preparing a semiconductor substrate; (b) forming a semiconductor film of amorphous substance on a main surface of the semiconductor substrate with an insulating film interposed therebetween; (c) introducing an impurity for lowering resistance into the semiconductor film; (d) introducing hydrogen ions or deuterium ions into the semiconductor film; (e) performing a heat treatment to polycrystallize the amorphous substance after the step (d); and (f) patterning the semiconductor film to form a gate electrode on the main surface of the semiconductor substrate with a gate insulating film interposed therebetween.
According to a second aspect of the present invention, in the method of manufacturing a semiconductor device of the first aspect further comprises the steps of: (g) selectively forming an isolation insulating film in the main surface of the semiconductor substrate; (h) introducing hydrogen ions or deuterium ions into the semiconductor substrate; (i) forming source/drain regions which are paired with the gate electrode interposed therebetween in the main surface of the semiconductor substrate within an element formation region defined by the isolation insulating film; and (j) forming metal-semiconductor compound layers on the source/drain regions.
According to a third aspect of the present invention, in the method of manufacturing a semiconductor device of the second aspect, the steps (d) and (h) are performed in the same process after the step (f).
According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device of any one of the first to third aspects further comprises the steps of: (k) forming extension regions which are paired with the gate electrode interposed therebetween in the main surface of the semiconductor substrate; and (l) forming semiconductor layers in which an impurity for lowering resistance is introduced on the extension regions.
According to a fifth aspect of the present invention, the method of manufacturing a semiconductor device comprises the steps of: (a) preparing a semiconductor substrate; (b) selectively forming an isolation insulating film in a main surface of the semiconductor substrate; (c) selectively forming a gate electrode on the main surface of the semiconductor substrate with a gate insulating film interposed therebetween within an element formation region defined by the isolation insulating film; (d) introducing hydrogen ions or deuterium ions into the semiconductor substrate; (e) forming source/drain regions which are paired with the gate electrode interposed therebetween in the main surface of the semiconductor substrate within the element formation region; and (f) forming metal-semiconductor compound layers on the source/drain regions.
According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device of the fifth aspect, the hydrogen ions or the deuterium ions are introduced at least in the vicinity of a corner defined by a bottom surface and a side surface of the isolation insulating film in the step (d).
According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device of the fifth aspect, the hydrogen ions or the deuterium ions are introduced at least in the vicinity of a corner defined by a side surface of the isolation insulating film and the main surface of the semiconductor substrate in the step (d).
According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device of the fifth aspect, the hydrogen ions or the deuterium ions are introduced in the main surface of the semiconductor substrate at least in the vicinity of an end portion of the gate electrode in the step (d).
According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device of any one of the fifth to eighth aspects, the step (f) has the steps of (f-1) forming metal films on the source/drain regions; and (f-2) performing a heat treatment to react the metal films with the source/drain regions, and wherein the heat treatment in the step (f-2) is performed under a hydrogen atmosphere or a deuterium atmosphere.
According to a tenth aspect of the present invention, the method of manufacturing a semiconductor device comprises the steps of: (a) preparing a semiconductor substrate; (b) selectively forming a gate structure on a main surface of the semiconductor substrate; (c) forming extension regions which are paired with the gate structure interposed therebetween in the main surface of the semiconductor substrate; and (d) forming semiconductor layers in which an impurity for lowering resistance is introduced on the extension regions.
According to an eleventh aspect of the present invention, in the method of manufacturing a semiconductor device of the tenth aspect further comprises the steps of: (e) introducing hydrogen ions or deuterium ions into the semiconductor layers; and (f) forming metal-semiconductor compound layers on the semiconductor layers after the step (e).
According to a twelfth aspect of the present invention, in the method of manufacturing a semiconductor device of the tenth or eleventh aspect further comprises the steps of: (g) forming sidewalls in contact with side surfaces of the gate structure after the step (d); and (h) ion-implanting an impurity into the semiconductor substrate with the gate structure and the sidewalls used as an implantation mask to form source/drain regions.
The present invention is also directed to a semiconductor device. According to a thirteenth aspect of the present invention, the semiconductor device comprises a semiconductor substrate; and a gate electrode of polycrystalline substance in which an impurity for lowering resistance is introduced, being selectively formed on a main surface of the semiconductor substrate with a gate insulating film interposed therebetween, and in the semiconductor device of the thirteenth aspect, the gate electrode includes a granular grain layer having a grain boundary not extending along a direction of film thickness of the gate electrode.
According to a fourteenth aspect of the present invention, the semiconductor device of the thirteenth aspect further comprises an isolation insulating film selectively formed in the main surface of the semiconductor substrate; a diffusion layer in which hydrogen or deuterium is diffused, being selectively formed in the semiconductor substrate; source/drain regions which are paired with the gate electrode interposed therebetween, being formed in the main surface of the semiconductor substrate within an element formation region defined by the isolation insulating film; and metal-semiconductor compound layers formed on the source/drain regions.
According to a fifteenth aspect of the present invention, the semiconductor device of the thirteenth or fourteenth aspect further comprises extension regions which are paired with the gate electrode interposed therebetween, being formed in the main surface of the semiconductor substrate; and semiconductor layers in which an impurity for lowering resistance is introduced, being formed on the extension regions.
According to a sixteenth aspect of the present invention, the semiconductor device comprises a semiconductor substrate; an isolation insulating film selectively formed in a main surface of the semiconductor substrate; a gate electrode selectively formed in the main surface of the semiconductor substrate with the gate insulating film interposed therebetween within an element formation region defined by the isolation insulating film; a diffusion layer in which hydrogen or deuterium is diffused, being selectively formed in the semiconductor substrate; source/drain regions which are paired with the gate electrode interposed therebetween, being formed in the main surface of the semiconductor substrate within the element formation region; and metal-semiconductor compound layers formed on the source/drain regions.
According to a seventeenth aspect of the present invention, in the semiconductor device of the sixteenth aspect, the diffusion layer is formed at least in the vicinity of a corner defined by a bottom surface and a side surface of the isolation insulating film.
According to an eighteenth aspect of the present invention, in the semiconductor device of the sixteenth aspect, the diffusion layer is formed at least in the vicinity of a corner defined by a side surface of the isolation insulating film and the main surface of the semiconductor substrate.
According to a nineteenth aspect of the present invention, in the semiconductor device of the sixteenth aspect, the diffusion layer is formed in the main surface of the semiconductor substrate at least in the vicinity of an end portion of the gate electrode.
According to a twentieth aspect of the present invention, the semiconductor device comprises a semiconductor substrate; a gate structure selectively formed in a main surface of the semiconductor substrate; extension regions which are paired with the gate structure interposed therebetween, being formed in the main surface of the semiconductor substrate; and semiconductor layers in which an impurity for lowering resistance is introduced, being formed on the extension regions.
According to a twenty-first aspect of the present invention, the semiconductor device of the twentieth aspect further comprises diffusion layers in which hydrogen or deuterium is diffused, being formed in the semiconductor layers; and metal-semiconductor compound layers formed on the semiconductor layers.
According to a twenty-second aspect of the present invention, the semiconductor device of the twentieth or twenty-first aspect further comprises sidewalls in contact with side surfaces of the gate structure, being formed on the semiconductor layers; and source/drain regions formed in a portion of the semiconductor substrate where neither the gate structure nor the sidewalls are formed.
In the method of the first aspect of the present invention, by introducing the hydrogen ions or the deuterium ions into the semiconductor film, a polycrystalline film at least partially having a granular grain layer can be formed through the heat treatment in the later step. The granular grain layer has a lot of grain boundaries extending multidirectionally, including a grain boundary not extending along the direction of film thickness of the polycrystalline film. Accordingly, the dopant introduced into the polycrystalline film is diffused multidirectionally along a lot of multidirectionally-extending grain boundaries in the granular grain layer. Therefore, the amount of dopant reaching an interface between the gate electrode and the gate insulating film can be reduced. As a result, it is possible to appropriately suppress variation in threshold voltage which is caused by the penetration of dopant, without lowering the impurity concentration in the gate electrode.
Further, when impurities such as oxygen, carbon and fluorine are mixed into the gate, by performing a heat treatment, these impurities are coupled to the hydrogen atoms or the deuterium atoms introduced into the gate, volatilizing, and thus the impurities can be removed from the gate. As a result, it is possible to suppress an increase in resistance of the gate electrode.
The method of the second aspect of the present invention can produce an effect of freeing up a distorted bond of the semiconductor atoms in a region where a stress is concentrated. This method also produces an effect of removing an impurity mixed into the source/drain regions with the hydrogen atoms or the deuterium atoms. Further, this method produces an effect of suppressing generation of an intruding portion of the metal-semiconductor compound layer in the vicinity of a portion below the gate insulating film or in the vicinity of an interface between the isolation insulating film and the semiconductor substrate. Furthermore, this method produces an effect of removing a native oxide film formed on the source/drain region with the hydrogen ions or the deuterium ions.
In the method of the third aspect of the present invention, since the step of introducing the hydrogen ions or the deuterium ions into the semiconductor film and the step of introducing the hydrogen ions or the deuterium ions into the semiconductor substrate are performed in the same process, a manufacturing process can be simplified as compared with a case where these steps are performed in different processes.
In the method of the fourth aspect of the present invention, since the semiconductor layer in which the impurity is introduced is formed on the extension region, it is possible to suppress an increase in sheet resistance of the extension region with the semiconductor layer of low resistance even when the extension region is formed shallower in the semiconductor substrate in order to suppress the short-channel effect.
In the method of the fifth aspect of the present invention, as the first effect, a bond of semiconductor atoms in the semiconductor substrate by the heat treatment and the semiconductor atoms are diffused so as to relieve a stress. At that time, the hydrogen atoms or the deuterium atoms introduced into the semiconductor substrate are coupled to some of the semiconductor atoms, to terminate an unsaturated bond. As a result, the distorted bond of the semiconductor atoms is freed up in a region where the stress is concentrated (in the vicinity of the corner defined by the bottom surface and the side surface of the isolation insulating film, in the vicinity of the corner defined by the side surface of the isolation insulating film and the upper surface of the semiconductor substrate and in the vicinity of the end portion of the gate electrode).
As the second effect, even when impurities such as oxygen, carbon and fluorine are mixed into the source/drain regions, by performing a heat treatment, the hydrogen atoms or the deuterium atoms introduced into the semiconductor substrate are coupled to these impurities, volatilizing, and thus the above impurities can be removed from the semiconductor substrate.
As the third effect, a hydrogen diffusion layer or a deuterium diffusion layer is formed in the vicinity of a portion below the gate insulating film and in the vicinity of the interface between the isolation insulating film and the semiconductor substrate. Since the silicidation reaction is suppressed in these regions as compared with other regions, it is possible to suppress generation of the intruding portion of the metal-semiconductor compound layer.
As the fourth effect, even when the native oxide film is formed on the exposed source/drain regions, the native oxide film is reduced by the hydrogen ions or the deuterium ions introduced into the semiconductor substrate, becoming H2O to volatilize.
For this reason, the native oxide film formed on the source/drain regions can be effectively removed. Therefore, it is possible to reduce the resistance value of the metal-semiconductor compound layer to be formed later on the source/drain regions.
In the method of the sixth aspect of the present invention, a distorted bond of the semiconductor atoms is freed up in a region where a stress is concentrated, specifically, in the vicinity of the corner defined by the bottom surface and the side surface of the isolation insulating film.
In the method of the seventh aspect of the present invention, a distorted bond of the semiconductor atoms is freed up in a region where a stress is concentrated, specifically, in the vicinity of the corner defined by the side surface of the isolation insulating film and the main surface of the semiconductor substrate.
In the method of the eighth aspect of the present invention, a distorted bond of the semiconductor atoms is freed up in a region where a stress is concentrated, specifically, in the vicinity of the end portion of the gate electrode.
In the method of the ninth aspect of the present invention, it is possible to increase the amount of hydrogen or deuterium remaining in the semiconductor substrate, not volatilizing, in the heat treatment.
In the method of the tenth aspect of the present invention, since the semiconductor layer in which the impurity is introduced is formed on the extension region, it is possible to suppress an increase in sheet resistance of the extension region with the semiconductor layer of low resistance even when the extension region is formed shallower in the semiconductor substrate in order to suppress the short-channel effect.
The method of the eleventh aspect of the present invention can produce an effect of freeing up a distorted bond of the semiconductor atoms in a region where a stress is concentrated. This method also produces an effect of removing an impurity mixed into the semiconductor layer with the hydrogen atoms or the deuterium atoms. Further, this method produces an effect of suppressing generation of an intruding portion of the metal-semiconductor compound layer in the vicinity of a portion below the gate insulating film and the like. Furthermore, this method produces an effect of removing a native oxide film formed on the semiconductor layer with the hydrogen ions or the deuterium ions.
In the method of the twelfth aspect of the present invention, by forming the source/drain regions, it is possible to further reduce the sheet resistance of the source and drain and achieve a still higher-speed operation.
In the semiconductor device of the thirteenth aspect of the present invention, the dopant introduced into the gate electrode is diffused multidirectionally along a lot of multidirectionally-extending grain boundaries in the granular grain layer in the process of manufacturing a semiconductor device. Therefore, the amount of dopant reaching the interface between the gate electrode and the gate insulating film can be reduced. As a result, it is possible to achieve a semiconductor device in which variation in threshold voltage which is caused by the penetration of dopant is suppressed.
The fourteenth aspect of the present invention can produce an effect of freeing up a distorted bond of the semiconductor atoms in a region where a stress is concentrated in the process of manufacturing a semiconductor device. This aspect of the present invention also produces an effect of removing an impurity mixed into the source/drain regions with the hydrogen atoms or the deuterium atoms. Further, this aspect of the present invention produces an effect of suppressing generation of an intruding portion of the metal-semiconductor compound layer in the vicinity of a portion below the gate insulating film or in the vicinity of the interface between the isolation insulating film and the semiconductor substrate. Furthermore, this aspect of the present invention produces an effect of removing a native oxide film formed on the source/drain regions with the hydrogen ions or the deuterium ions. Therefore, it is possible to achieve a semiconductor device whose leakage current is reduced.
In the semiconductor device of the fifteenth aspect of the present invention, since the semiconductor layer in which the impurity is introduced is formed on the extension region, it is possible to suppress an increase in sheet resistance of the extension region with the semiconductor layer of low resistance even when the extension region is formed shallower in the semiconductor substrate in order to suppress the short-channel effect.
The sixteenth aspect of the present invention can produce an effect of freeing up a distorted bond of the semiconductor atoms in a region where a stress is concentrated in the process of manufacturing a semiconductor device. This aspect of the present invention also produces an effect of removing an impurity mixed into the source/drain regions with the hydrogen atoms or the deuterium atoms. Further, this aspect of the present invention produces an effect of suppressing generation of an intruding portion of the metal-semiconductor compound layer in the vicinity of a portion below the gate insulating film or in the vicinity of the interface between the isolation insulating film and the semiconductor substrate. Furthermore, this aspect of the present invention produces an effect of removing a native oxide film formed on the source/drain regions with the hydrogen ions or the deuterium ions. Therefore, it is possible to achieve a semiconductor device whose leakage current is reduced.
In the semiconductor device of the seventeenth aspect of the present invention, a distorted bond of the semiconductor atoms is freed up in a region where a stress is concentrated, specifically, in the vicinity of the corner defined by the bottom surface and the side surface of the isolation insulating film.
In the semiconductor device of the eighteenth aspect of the present invention, a distorted bond of the semiconductor atoms is freed up in a region where a stress is concentrated, specifically, in the vicinity of the corner defined by the side surface of the isolation insulating film and the main surface of the semiconductor substrate.
In the semiconductor device of the nineteenth aspect of the present invention, a distorted bond of the semiconductor atoms is freed up in a region where a stress is concentrated, specifically, in the vicinity of the end portion of the gate electrode.
In the semiconductor device of the twentieth aspect of the present invention, since the semiconductor layer in which the impurity is introduced is formed on the extension region, it is possible to suppress an increase in sheet resistance of the extension region with the semiconductor layer of low resistance even when the extension region is formed shallower in the semiconductor substrate in order to suppress the short-channel effect.
The twenty-first aspect of the present invention can produce an effect of freeing up a distorted bond of the semiconductor atoms in a region where a stress is concentrated. This aspect of the present invention also produces an effect of removing an impurity mixed into the semiconductor layer with the hydrogen atoms or the deuterium atoms. Further, this aspect of the present invention produces an effect of suppressing generation of an intruding portion of the metal-semiconductor compound layer in the vicinity of a portion below the gate insulating film and the like. Furthermore, this aspect of the present invention produces an effect of removing a native oxide film formed on the semiconductor layer with the hydrogen ions or the deuterium ions. Therefore, it is possible to achieve a semiconductor device whose leakage current is reduced.
In the semiconductor device of the twenty-second aspect of the present invention, by forming the source/drain regions, it is possible to further reduce the sheet resistance of the source and drain and achieve a still higher-speed operation.
A first object of the present invention is to provide a method of manufacturing a semiconductor device and a structure of the semiconductor device, which can appropriately suppress variation in threshold voltage which is caused by the penetration of dopant without lowering an impurity concentration in a gate electrode. A second object of the present invention is to provide a method of manufacturing a semiconductor device and a structure of the semiconductor device, which can reduce leakage currents at gate, source and drain by avoiding generation of the intruding portion of a metal silicide at an interface between an offset film of the gate electrode and a silicon substrate or an interface between an STI and the silicon substrate. A third object of the present invention is to provide a method of manufacturing a semiconductor device and a structure of the semiconductor device, which can improve the current driving capability of a MOSFET by suppressing an increase in sheet resistance of an extension region even when the extension region is formed shallower in the silicon substrate.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.